This invention relates to dynamic random-access memories (DRAMS).
In a DRAM, the contents of the memory gradually decay, and it is necessary to refresh the memory periodically in order to preserve its contents. This normally involves cycling through the memory and performing a read/write operation on each location of the memory in turn. Typically, each location must be refreshed every 4 milliseconds.
If the system in which the DRAM is used is switched off (powered down), then the contents of the DRAM may be lost. This can be avoided by providing some form of battery back-up for the memory, so that refreshing can continue even when the system is powered down.
It has been proposed to provide a dynamic random-access memory having a first refresh circuit for producing memory refresh cycles during a power-up condition, and a second refresh circuit for producing memory refresh cycles during a power-down condition and having a lower power requirement than the first refresh circuit. This enables the power requirements in the power-down conditions to be reduced, so as to avoid excessive drain on the battery.
When two refresh circuits are used in this way, it is necessary to switch between the two circuits when power is removed or restored. A problem arises in that, when power is restored, it is necessary to bring the power-up refresh circuit into operation quickly, to avoid loss of data. This may be difficult to achieve, since it may be necessary for a system processor to initialise the power-up refresh circuit before it can begin to operate.